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PCD8 8-bit DMA Interface User’s Guide About the Software and Firmware

EDT, Inc. May 2007 2

•The PCI FPGA communicates with the host computer over the PCI Bus. It implements the DMA

engine, which transfers data between the board and the host computer, and loads its firmware on

powerup from flash ROM located on the main board.

•The UI FPGA transfers data between the user device and the PCI FPGA; in some instances, it

also sends the data to the mezzanine board. The UI FPGA or mezzanine board may also process

the data in some manner, depending on the application.

When data comes in from the user device, the UI FPGA sends it to input and output FIFO buffers,

which smooth data transfer between the user device and the PCI Bus, as well as accommodating data

during the transition from one DMA to the next. Host DMA transfers are queued in hardware,

minimizing the amount of FIFO required.

To ensure maximum throughput, EDT’s DMA library, the DMA driver, and the FPGA configuration files

all support pipelining.

• The library routines as well as the driver preallocate kernel resources for DMA (for example, mem-

ory), rather than waiting for an application to request a DMA transfer (typically with an EDT library

routine call such as

edt_read, edt_write, or edt_start_buffers). When one DMA transfer

ends, the resources remain allocated and available for use by the next DMA transfer.

• A portion of host memory can be configured as ring buffers: a set of buffers preallocated for DMA

and reused in round-robin fashion.

• The FPGA fabric provides two sets of DMA registers, so that when one DMA transfer starts, the

registers required for the next are already prepared, thus enabling zero-latency transitions be-

tween DMA transfers.

You can set the number of ring buffers and their size with the EDT DMA library call

edt_configure_ring_buffers. Configure the ring buffers according to your application’s DMA

requirements — a useful configuration is often four one-megabyte ring buffers. Four ring buffers allow

one to be used for the current DMA transfer, one for pending DMA, and one for the application, with

one extra to ensure zero-latency transitions.

You can fine-tune your application to the latency requirements of a particular system by increasing or

decreasing the size of the ring buffers; slow systems may need larger ring buffers, while fast systems

may achieve better performance with more smaller ones.

Some host systems may restrict your ability to allocate particularly large ring buffers, or particularly

large numbers of them. For example, some Windows systems limit DMA resources to a maximum of

64 MB in all. If you suspect this might be a problem in your system, be sure that your code checks for

error returns after calling

edt_configure_ring_buffers and before calling edt_start_buffers.

About the Software and Firmware

Install the PCD8 hardware and software according to the instructions on the software CD sleeve, using

one of the firmware files listed below:

pcda8.bit UI Xilinx configuration file for 8-bit parallel dual-channel input/output for the PCI CDa or the

PCI SS/GS.

pcd8_src.bit UI Xilinx configuration file for 8-bit parallel dual-channel input/output for the

PCI CD.

xtest.bit UI Xilinx configuration file for running the test described in the section entitled

Testing in the PCI CD/CDa User’s Guide.

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