CDA CD 60 Especificações descarregar pdf (Página 5)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 5

Overview

The PCI Bus Configurable DMA (PCI CD) board is a single-slot, 16-bit parallel input/output interface

for PCI bus-based computer systems. It is designed for continuous input or output between a user

device and PCI bus host memory. This interface is typically used to move data between a PCI bus host

computer and devices such as scanners, plotters, imaging devices, or research prototypes. The PCI CD

uses a simple synchronous protocol for transferring data.

The CDa is very similar to the PCI CD, with the following differences:

• The PCI CDa uses the PCI SS-style phase-locked loop (PLL) and DMA engine.

• The PCI CDa comes standard with an XC2S100e user interface Xilinx; an XC2S600e Xilinx is

optional.

• The PCI CD I/O is either RS422 or LVDS.

• FIFOs are internal to the Xilinx FPGA.

• The PCI CDa will operate in 66 MHz PCI slots with transfer rates up to 210 megabytes per second.

It uses the same host software as the PCI CD.

Features

• The PCI CD/CDa supports scatter-gather Direct Memory Access (DMA) in hardware, adapting to

the memory management model of the host architecture. It includes a software driver and software

library that enable applications to access the PCI CD/CDa and transfer data continuously or in

bursts across the PCI CD/CDa interface using EDT library calls.

• The interface is synchronous, meaning all data and control signals are transmitted with a clock

signal. Either the PCI CD/CDa interface or the external device can generate receive or transmit

timing, or each can generate its own transmit timing.

• The PCI CD/CDa RS422 oscillator operates at 10 MHz or 20 megabytes per second. The PLL can

be selected as the clock source, which can be programmed at various speeds. The transfer rate is

limited by the RS422 interface.

• The PCI CD PECL (PCI CD-40) oscillator operates at 20 MHz or 40 megabytes per second. The

PLL can be selected as the clock source, which can be programmed at various speeds. The transfer

rate is limited by the PECL interface.

• The PCI CD/CDa LVDS oscillator operates at 30 MHz or 60 megabytes per second. The clock

operates at various speeds depending on programming. The transfer rate is limited by the LVDS

interface.

• The DMA Engine on all PCI CD boards is up to 80 megabytes per second. The DMA engine on all

CDa boards is up to 210 megabytes per second.

• All CD/CDa boards use 4 KB input and output FIFOs, and all signals are differential.

• The input and output FIFO buffers smooth data transfer between the PCI bus and the user device,

accommodating data during the transition from one DMA to the next. DMA transfers are queued in

hardware, minimizing the amount of FIFO required.

This manual describes the operation of the PCI CD/CDa with the UNIX-based and Windows operating

systems.

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