CDA CD 60 Especificações descarregar pdf (Página 85)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 85

Stat Register

Size 8-bit

I/O read-only

Address 0x03

Access PCD_STAT

Bit PCD_ Description

D0-3 STAT The state of user-definable STAT input signals as last

sampled by the RXT clock signal.

D4-7 STAT_INT Interrupt bits for the status bits. If the following conditions

are both true, then the corresponding bit of these four can

be asserted to cause a PCI Bus interrupt:

• The device interrupt is enabled using the

RMT_EN_INTR bit in the PCI Interrupt and Remote

Xilinx Configuration register.

• The corresponding bit is asserted in the command

The PCI Bus interrupt is then caused when the

corresponding STAT signal is asserted according to the

polarity specified in the stat polarity register. To reset the

interrupt, disable and re-enable the appropriate

STAT_INT_EN bit in the command register.

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 91

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