CDA CD 60 Especificações descarregar pdf (Página 90)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 90

Output Data Valid Delay Register (PCI CDa only)

Size 8-bit

I/O read-write

Address 0x28

Access ODV_DELAY

Bit Name Description

7-0 ODV_DELAY Set this register to the number of 16-bit words to hold off

output. Outgoing data backs up in FIFO, reducing or

eliminating ODV transitioning on start up.

LED Control Register

Size 8-bit

I/O read-write

Address 0x30

Access LED_CTL

Bit Name Description

1-0 LED0

LED1

Set according to the following table to select what drives

the LED:

LED1 LED0 Source

0 0 From LED signal. If you choose this

source, you must also set bit 2 in this

0 1 IDV

1 0 DNR

1 1 RXT

2 LED2 Set to 1 to turn LED on, only when LED0 and LED1 are set

to 0 (see above chart).

1 2 ... 85 86 87 88 89 90 91

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CDA CD 60 Especificações Página 90