CDA CD 60 Especificações descarregar pdf (Página 64)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 64

Signal PCI CD I/O Description

data after DNR is presented to the input pins.

Table 4. Signals

Timing

The clock and data output timing is specified at the pins of the PCI CD/CDa connector.

PCI CD-20 PCI CD-40 PCI CD-60

Clock frequency 0-10 MHz 0-20 MHz 0-30 MHz

Clock duty cycle 50% ± 10 ns 50% ± 5 ns 50% ± 5 ns

Input minimum setup time 20 ns 5 ns 5 ns

Input minimum hold time 25 ns 6 ns 6 ns

Output maximum propagation delay 20 ns 10 ns 10 ns

Table 5. Timing Specifications

The following figure shows the PCI CD timing:

Typical DMA data read handshake

Input FIFO gets almost full and then empties

FROM DEVICE TXT

FROM DEVICE DNR

FROM DEVICE IDV

FROM DEVICE DAT (IN)

FROM PCI CD TXT

FROM PCI CD BNR

Typical DMA data write handshake

User device needs to hold data out

FROM PCI CD TXT

Typical data output startup

User device is ready (DNR = FALSE)

The number of ODV deassertion depends on the frequency of the TXT clock and

the PCI BUS response of the host.

To minimize or prevent ODV deassertions, align the memory buffer so data is

transferred from a 64 byte boundary. Then the first PCI BUS transfer will be in

burst mode.

FROM PCI CD TXT

FROM DEVICE RXT

FROM DEVICE DNR

FROM PCI CD BNR

FROM PCI CD ODV

FROM PCI CD BNR

FIFO495 FIFO496

FIFO497

FIFO498

FIFO499 FIFO500

FIFOxxx

+3 +4 +5

FROM PCI CD DAT (OUT)

DATA N + 1

+4 +5

+9 +10 +11

FROM PCI CD DAT (OUT)

DATA 0

1 234

91011

FROM DEVICE DNR

Figure 6. Timing Specifications

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 90 91

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