CDA CD 60 Especificações descarregar pdf (Página 8)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 8

To reselect the default Xilinx bitfile at a later time, rerun pcdrequest, or edit the pcdload script

file by hand.

Note: xtest downloads its own test bitfile automatically; after running xtest, run pcdload to

reload the default bitfile.

The PCI CD/CDa boards are synchronous interfaces—they send a clock signal with all data and control

signals. The PCI CD stores inputs only at the rising edge of the receive timing (RXT) signal that comes

from the user device. The user device stores outputs from the PCI CD only at the rising edge of the

transmit timing (TXT) signal. The PCI CD/CDa always outputs the TXT signal, but the internal source

of the signal can be either the RXT from the user device or an internal oscillator on PLL in the PCI

CD/CDa. If an internal oscillator is used, its rate is 10 MHz for the PCI CD/CDa RS422, 20 MHz for

the PCI CD PECL, and 30 MHz for the PCI CD/CDa LVDS.

Configuration Utility: initpcd

EDT supplies a board configuration utility with your PCD driver called initpcd. This utility inputs a

simple text configuration file to set up the PCI CD/CDa boards, as well as any other board that uses the

PCD driver. Use initpcd to reliably and consistently configure your PCD boards and to eliminate

messy configuration code from your applications.

Complete documentation of the initpcd command set is included as the first comment in the source

file initpcd.c. Several .cfg files are also included in the PCD driver directory as examples.

A typcial initpcd .cfg script performs the following operations:

• Loads a specified firmware bitfile.

• Sets clock speeds on available PLL clocks.

• Sets any configuration registers, such as channel enable and direction bits, DMA mapping

registers, and any other arbitrary register, including customer-defined registers.

• Sets bit order, byte order, and short word order supported in the EDT firmware.

• Flushes the user interface FIFO to initialize the user interface firmware.

The following is an example of a simple PCI CDa configuration file:

bitfile: pcda.bit

# Enable interface Xilinx

command_reg: 0x08

# Enable and set the onboard PLL clock generator to 30MHz

funct_reg: 0x80

run_command: set_ss_vco -F 30000000.0 0

# Alternatively setting interface register 0x0f to 0x02 sends

RXT to TXT.

intfc_reg: 0x0f 0x00

#intfc_reg: 0x0f 0x02

# Byteswap and shortswap usually 1 for Sun, 0 for Intel.

byteswap_sun: 1

shortswap_sun: 1

byteswap_x86: 0

shortswap_x86: 0

flush_fifo: 1

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 90 91

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