
PCI CD/CDa Configurable DMA Interface User’s Guide Hardware Interface Protocol
EDT, Inc. May 2007 15
Timing
The clock and data output timing is specified at the pins of the PCI CD/CDa connector.
Figure 4 shows the PCI CD/CDa timing.
Table 2. Timing Specifications
PCI CD-20 PCI CD-60 PCI CDa LVDS PCI CDa RS-422
Clock frequency 10 MHz 30 MHz 40 MHz, or as
programmed
10 MHz, or as
programmed
Clock duty cycle 50% ±10 ns 50% ± 5 ns 50% ± 5 ns 50% ± 5 ns
Input minimum set-up time 20 ns 5 ns 5 ns 20 ns
Input minimum hold time 25 ns 6 ns 6 ns 25 ns
Output maximum propagation delay 20 ns 10 ns 10 ns 20 ns
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