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PCI CD/CDa Configurable DMA Interface User’s Guide Registers

EDT, Inc. May 2007 23

Scatter-gather DMA Next Address Register

Size 32-bit

I/O read-write

Address 0x14

Access EDT_SG_NXT_ADDR

Comment The driver software writes this register as described in step 2 of the list on

page 21.

Scatter-gather DMA Current Count and Control Register

Size 32-bit

I/O read-only

Address 0x18

Access EDT_SG_CUR_CNT

Comment The driver software can read this register for debugging or to monitor DMA

progress.

Scatter-gather DMA Next Count and Control Register

Size 32-bit

I/O read-write

Address 0x1C

Access EDT_SG_NXT_CNT

Comment The driver software writes this register as described in step 3 in the list on page 21.

Bit Description

31–0 The starting address of the next DMA.

Bit Description

31-16 Read-only versions of bits 31–16 of the Scatter-gather DMA next count and control register.

15–0 The number of words still to be transferred in the current DMA.

Bit EDT_ Description

31 EN_RDY Enable scatter-gather next empty interrupt. A value of 1 enables DMA_START (bit 29

of this register) to set DMA_INT (bit 12 of the Status register), thus causing an interrupt

if the PCI_EN_INTR bit is set (bit 15 of the Main DMA Command and Configuration

A value of 0 disables the DMA_START from causing an interrupt.

30 DMA_DONE Read-only: a value of 0 indicates that a scatter-gather DMA transfer is currently in

progress. A value of 1 indicates that the current scatter-gather DMA is complete.

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