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Hardware Interface Protocol PCI CD/CDa Configurable DMA Interface User’s Guide

16 EDT, Inc. May 2007

Figure 4. PCI CD/CDa Timing

The number of ODV deassertions depends on the frequency of the TXT clock and the PCI Bus

response of the host. To minimize or prevent ODV deassertions, align the memory buffer so that data

is transferred from a 64-byte boundary. In that case, the first PCI Bus transfer is in burst mode.

from device RXT L

from device DNR L

from device IDV H

from device DAT

(IN)

from CD/CDa TXT L

from CD/CDa BNR L

Typical DMA data read handshake — input FIFO gets almost full, then empties:

Typical DMA data write handshake — user device needs to hold data out:

from CD/CDa TXT L

from CD/CDa BNR L

from CD/CDa ODV H

from CD/CDa DAT

(OUT)

from device RXT L

from device DNR L

Typical data output startup— user device is ready (DNR = false):

from CD/CDa TXT L

from CD/CDa BNR L

from CD/CDa ODV L

from CD/CDa DAT

(OUT)

from device RXT L

from device DNR L

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